The Amplifier Design Wizard features are shown for each main module:
The Analysis Module (document type .ani) provides for extended cascade analysis and nodal analysis, including cascade and nodal noise and power analysis. ADW circuits can also be tuned or optimized in the Analysis Module. Direct optimization and optimization by re-synthesis are provided for. When the power performance is optimized, margins can also be set on the maximum unclipped output power of the drivers used in a multistage amplifier. (The option to constrain the output power to be inside a specified window can be used to design limiting amplifiers.) Integrated artwork (microstrip and stripline) and schematic capabilities are provided in the Analysis Module. The circuit can be edited schematically and also in the artwork and text editing sections. Topology changes should be made in the schematic or the text editing sections, but components may be deleted in artwork section.
The power analysis features include calculation of the maximum unclipped output power and estimation of the gain compression. The maximum unclipped output power is the power level just before the onset of clipping in the intrinsic output current or voltage of a transistor. Compression calculations assume a fixed difference between the saturated output power and the maximum unclipped output power at the specified DC operating point. This difference can be specified by the user.
The S-parameters, the noise parameters, the input and output VSWRs, the Rollette and Sterne stability factors (k ; K), the source and load stability factors (SSF, LSF; extended versions of mu and mu-prime as defined by Edwards and Cheng), the series or shunt resistance required to stabilize the circuit at each frequency of interest, the tunability, the MAG, the MSG, the operating power gain and the available power gain of the circuit are also calculated.
When current-series feedback and/or voltage-shunt feedback is applied to a two-port, the Analysis Module can be used to calculate the open-loop and feedback impedances, the loop gain and the effective load termination provided to the two-port. With this information, the gain and phase margins for stability can be calculated for each stage in an amplifier. The reflection gain at any point can also be calculated by using the commands provided for this purpose. The oscillation | resonance frequency and the slope in the phase response at this frequency are also calculated automatically in both cases. A command to simplify the design of the resonator circuit in an oscillator was also implemented. If voltage-shunt and current series feedback are used in a single stage, the loop gain of each loop is calculated. The loop gain and reflection stability analysis capability is provided as a separate option.
The capability to analyze transmission-line transformers (low frequency response included), as well as single-layer parallel-plate capacitors is provided in the software. Conventional transformers can also be used. (A model for a three-winding transformer is also provided.) The transformer capability combined with the power and noise analysis capability can be used to design high dynamic range Norton-type lossless feedback transformer amplifiers. Commensurate n-section stepped line resistive transformers can also be designed and inserted automatically any at point in an ADW schematic.
Integrated ASCII text editing and schematics editing capabilities are provided. The topology of the cascade circuit and the values of the associated components can be edited on the schematic displayed. Topology changes can also be made via the netlist or by re-synthesizing a network or re-modifying a transistor stage. Line dimensions can be modified in the artwork section.
Several files can be open at the same time and data can be transferred between them (text editing or schematic views).
Wizards are provided to automatically set up various impedance-matching problems in the Analysis Module. In each case the circuit is split into two sections at the position marked by the command.
The IIM Wizard is provided for setting up an interstage impedance-matching problem with each section terminated with the actual terminations of the circuit (the load or the source impedance specified). The "RMT" and the "LMT" commands are similar, but in the first case the right-hand section is terminated with the MAG termination instead of the actual load termination and in the latter case the left-hand section is terminated with its MAG termination.
The IVI Wizard is used to set up an impedance-matching problem to improve the input VSWR of the left-hand section and to level the gain of the circuit at the same time. This command is often used to improve the input VSWR of a low-noise amplifier without degrading the noise figure of the input (left-hand) section.
The OVI Wizard is provided for improving the output VSWR of the output (right-hand) section and to level the gain of the circuit. This command is often used to improve the output VSWR of a power stage.
All of these matching problems are set up to level the overall transducer power gain of the circuit. When required, a conjugate match can be approximated by changing the power gain required from the passive network to be synthesized to unity.
The impedance-matching module is required to synthesize the required matching network. The synthesized solution is inserted automatically into the relevant circuit file, at the previously marked position.
Transistor parameters can be imported from Touchstone "*.s2p" files into an ADW circuit file by using the Two-port Wizard provided.
The "MOT" command is provided to set up and solve device-modification problems (designing feedback and loading networks to pre-condition a transistor for improved performance before the matching networks are synthesized). If a stage is re-designed by using the MOT command, the associated matching networks can be removed or can be left in place. The Device Modification Module is required to do the modification and the Impedance-Matching Module is required to re-synthesize any matching networks removed.
Apart from optimization by re-synthesis, an ADW circuit can also be optimized directly to meet a set of target specifications. Variables can be marked easily on the schematic (or in the text editing section) for direct optimization. Optimization features are also provided to fit a model to a set of measured S-parameters.
In addition to the re-synthesis commands, several design commands are provided in the Analysis Module. These include commands to
Oscillations can start up because of the loop gain or the reflection performance of an oscillator or an amplifier stage. The “REFL” and “IREF” commands can be used to compare the reflection coefficients to the left and to the right of the position at which the command is inserted. The comparison can be made on a Smith Chart or on a rectangular plot.
An S-parameter data file (Ampsa .spi format or TouchstoneTM .s2p format) for the circuit analyzed can also be created. This makes complex modification schemes possible, and also allows for synthesizing a lossy matching network for the circuit analyzed by using the Device Modification Module.
When an S-parameter data file is created, a power parameter file (type "*.map", "*.ma2", "*.ma3", "*.ma4") can now be created for the complete circuit (or an equivalent circuit not supported). The "*.map" file is created for the first transistor listed in the file (usually the transistor closest to the load), the "*.ma2" for the next, ... This capability is used to control/predict the power provided by a transistor when one of the standard small-signal models does not apply. The power parameter files created can be used to calculate the expected power performance or to generate power contours and to set up the associated matching problem by using the "User-specified power parameters" option provided in the S-parameter module instead of specifying the components of one of the small-signal models supported.
The results obtained (s11 , s21 , s22 , 1/s11* , 1/s22* , the optimum noise impedance, the transducer power gain, phase shift, noise figure, VSWRs, the loop gain, the associated transistor load termination and the expected output power) can be displayed graphically.
Zoom and offset capabilities are provided when the results are displayed on a Smith Chart. The vertical axis of rectangular plots can be re-scaled by the user. The horizontal axis can be re-scaled by using the option to modify the passband. The performance of up to two nodal blocks can also be displayed graphically with that of the main circuit by adding the "Graphics" command in the line defining the name of the nodal block. Variations of the “graphics” command are also provided.
Any schematics or graphics can be plotted to a file in HPGL or DXF format after which it can be imported into most graphics programs. The schematic of the complete circuit can also be processed in this way.
When the circuit is transformed into microstrip or stripline form, the line lengths are adjusted to compensate for the shifts in reference planes associated with the discontinuities. The lines can also be tapered at the junctions to reduce the discontinuity effects. The artwork can be displayed and modified graphically in the Analysis Module.
Note that lumped elements and transistors are displayed schematically on the artwork. The associated labels are displayed too and can be moved around by left-dragging it with the mouse. The lumped element values can be edited in the schematic view (the schematic and the artwork can be linked). The gap or the offset spacing used for a lumped element can be edited in the artwork section.
The artwork modification features include automatic termination of any shorted stubs with via holes (single via in a rectangular pad), controlling whether stubs will point upwards or downwards, curving or meandering lines, adding specified gaps or offsets for the lumped components used, defining the positions and the orientation of the connections to be made to the transistors used and allowing for current-series feedback when a transistor has two source connections. A part of a (or a complete) line can also be hidden on the artwork by using the Cut Option when the line dimensions are edited (This is useful when a line is only required for simulation purposes). The connections to a coil can be made in line with the length direction or perpendicular to it. Outlines to show the coil size and position are also created. Vector information on the nodes of any selected component can also be obtained.
Any loops (voltage-shunt feedback or series block loops) in the artwork should be closed properly. Once the angular alignment is resolved, a loop can be closed automatically in the artwork section. Loops can be closed by adjusting the dimensions of line or a thin film resistor, or by adjusting the gap or the offset vector associated with a lumped component.
An ADW circuit file can be exported as a Super CompactTM or a TouchstoneTM nodal analysis file, or a schematic script can be created for Microwave OfficeTM. The script can be created for the ADW schematic or for the artwork. The ADW artwork can also be exported in Sonnet Software® format or in DXF or HPGL format. When the circuit is exported in DXF format a technology file is also created for CST's Microwave StudioTM. This file is use to extract the different DXF layers at the correct elevation with the correct thickness. The DXF layers are also mapped to the corresponding CST materials.
The Impedance-Matching Module (document type .mmi) is used to synthesize lumped-element, distributed or mixed lumped/distributed matching networks. Commensurate (equal line length) and non-commensurate networks can be synthesized. When non-commensurate networks are designed, the line widths are set by the user. The line lengths are fixed when commensurate networks are synthesized. When commensurate networks are synthesized, different lengths can be set for the main-line sections, the open-ended stubs and the short-circuited stubs. Connecting lines can be added in both cases to the input and the output ports to ensure that all the networks synthesized will effectively start and end with series elements.
When commensurate networks are synthesized, the lowest and highest characteristic impedances allowable and the length of the commensurate lines must be specified (variable characteristic impedances, fixed line lengths). Similar to the line lengths, different constraints can be imposed on the characteristic impedances of the main-line sections and the open-ended and short-circuited stubs. The length option can be used to force the lengths of any stubs used to be electrically short. The stub impedance/susceptance will approximate that of the equivalent lumped component closely if this is done. This opens the possibility of replacing the stubs required in the synthesized solutions with lumped components or with stubs of different width or length (The Equivalent Stub Command provided in the Analysis Module can be used for this purpose).
When non-commensurate distributed solutions are synthesized, fixed characteristic impedances or line widths are used for the distributed solutions (variable line lengths). As mentioned above, the characteristic impedances | lines widths to be used must be specified by the user (In general, the characteristic impedance used for the main-line sections and the short-circuit stubs should be high, and that for the open-ended stubs should be low). The characteristic impedance of the main-line sections can be different from that of the shorted stubs and the open-ended stubs. The widths of the main-line sections can be also be tapered. The line lengths are used as variables, but the lengths of the different main-line sections can be constrained. The minimum length must be long enough to provide the physical separation required to prevent overlap and to prevent coupling between the stubs. When a microstrip solution is required, a rendering of the line widths and the minimum length of the main-line sections is displayed graphically for verification purposes. The electrical parameters associated with the width and length specifications, and the associated T-junctions, are also calculated and can be displayed.
When mixed lumped/distributed networks (non-commensurate) are synthesized, the distributed synthesis approach is followed too, but the line lengths are reduced by using inductors and/or capacitors when the required values are within the constraints specified. The options to reduce the lengths of open-ended stubs and/or shorted stubs and/or the main-line sections are provided. Options are also provided to replace any shunt capacitors required with overlay capacitors, or any open-ended stubs required with stepped transmission-line sections. The stepped transmission-line option is useful when matching networks for power amplifiers are synthesized. Pads can also be specified for the lumped components used in distributed solutions. An extra connecting line can also be specified for stubs (This option can be used to separate the shunt component pad from the main-line junction, mainly for solder reflow purposes). A rendering of the pad sizes specified is also displayed graphically for verification purposes.
When mixed lumped/distributed networks (non-commensurate) are synthesized, pads can be specified for the lumped elements. Parasitic inductance | capacitance can also be specified for the capacitors | inductors used. The parasitic phase shift associated with the gap of a chip capacitor (horizontal mounting) can also taken into account during synthesis. The option to terminate any short-circuited stubs used with single hole vias or by using inductors (bond wires) is also provided.
Each matching problem must be specified in real-frequency format. Data can also be imported from "*.s1p" or "*.s2p" files. Note that the gain in matching problems can now be set equal to, greater than or smaller as the specified gain value. The smaller as option is useful when the matching network is used for suppression (filtering) too.
The target impedance at each frequency can be a point inside the Smith Chart (point-match), any point on the circumference of a Smith Chart circle (circle match), or the area inside or outside such a circle. The circles of interest could be constant gain or constant noise figure circles, or circular approximations of areas defined by load-pull measurements.
Control over the input or output impedance of the matching network at the 2nd and 3rd harmonic frequencies is provided. A Smith chart sector or a segment on the edge of the Smith chart can be set as target at each harmonic frequency. When reactance values are targeted, control over the resistance at the harmonics frequencies is also provided in order to minimize power generation at these harmonic frequencies. A harmonic sector is defined by two intersecting lines and the Smith chart edge.
Harmonic traps can be introduced in the design via fixed-element sections added to the matching network. Information on potential second-harmonic and third-harmonic traps is provided during the load-pull phase. The viability of these traps is also considered- Significant loading at the fundamental frequencies should be avoided.
The synthesis algorithm for non-commensurate networks was augmented to introduce second-harmonic and/or third-harmonic traps in the synthesized networks. A shunt capacitive branch in a matching network can now control the fundamental-frequency performance and can also provide resonance at the transmission-null frequency targeted. This also applies to lumped capacitors or inductors. Each shorted stub branch can also be complemented with an open-ended stub branch for dual control. Different trap frequencies can be specified for the open-ended and the shorted stub branches.
Wizards were implemented in the Impedance-Matching Section for setting up the specifications for distributed | microstrip solutions.
Solutions to the matching problem defined are synthesized by doing synthesis-based systematic searches, followed by finer searches and then optimization of the best solutions found. The systematic search can be done globally over the different topologies or can be restricted to low-pass or high-pass topologies, or topologies without any series capacitors or without any shunt inductors. The option to use topologies suitable for inter-stage biasing (four or more element are required in this case) is also provided. These constraints are only active during the search phase.
When matching networks are designed to control the active performance of an amplifier stage, the option to optimize the active performance is provided when solutions have been synthesized to the equivalent passive problem.
Solutions can be displayed or printed or copied to the clipboard. When microstrip solutions are required, the artwork of each solution can also be displayed. The input and output impedance of each matching network can be displayed graphically or in tabular form.
When the harmonic impedances were controlled, the impedance at the harmonic frequencies can also be displayed. When the load network for a power stage is designed, the matching network input impedance, as well as the associated intrinsic impedance presented to the transistor can be displayed graphically. The intrinsic impedances are generally of much creater interest than the external impedances.
A worst-case tolerance analysis is done on the solutions provided. Preference should be given to insensitive solutions.
The solution selected can be exported as an ADW circuit file, in TouchstoneTM or Super CompactTM netlist format, DXF format (artwork only) or HPGL format (artwork only). Microwave OfficeTM scripts can also be created for the solutions synthesized.
When a problem was defined by using one of the Analysis Module Wizards, the solution selected can be inserted automatically at the correct position in the ADW circuit file. The Undo Command in the Analysis Module can be used to remove the inserted solution, if required. This option can be used to set up circuit files with different matching networks.
The Modeling and Modification Network Module (document type .spi) can import S-parameters and noise parameters from TouchstoneTM "*.s2p" files. It can also be used to fit models to the small-signal parameters specified for FETs, HEMTs or bipolar transistors.
Models are fitted by initialization and optimization. Package parasitics can be specified and can be included in the optimization. Any of the variables can be specified to be fixed or constrained when the optimization is done.
The model specified or fitted is used to calculate a set of parameters (power parameters) to map the external transistor voltages to the intrinsic voltages and to map the intrinsic output current to the intrinsic voltages. By using these parameters, the intrinsic load-line of the transistor can be controlled easily and the power performance can be estimated for Class A and also class B stages. The effect of any feedback or loading added in the device-modification section can also be determined when power parameter are used. Linearity is assumed when the power parameters are calculated.
Power parameters for models not supported by the ADW can be calculated by using the capabilities provided in the Analysis Module (only linear models can be created). These parameters can then be saved to a file (file type .map) and will be used to calculate the power performance. When the power parameters are used directly, a model should not be fitted to the transistor in the Modeling and Modification Network Module. Any model (file type .mdl) fitted previously should be deleted.
Interpolation capabilities (linear, and three- or four-point spline curve fitting) and editing capabilities are provided in the Modeling and Modification Module. The model fitted should be used to extrapolate the data. It should also be used for interpolation when sufficient data are not provided.
The S-parameters and noise parameters specified or imported can be transformed to those corresponding to different transistor configurations (common source/emitter; common gate/base; common drain/collector). Any power parameters specified are also modified when the configuration is changed.
The default source or load impedance for the amplifier is assumed to be 50 Ohm. Complex terminations can also be specified by using the MOT Wizard provided in the Analysis Module.
Artwork vectors defining the position and orientation of the connections to be made to the transistor must also be defined in the Modeling and Modification module. The defined values are displayed graphically for verification purposes.
If the power performance is of interest, the parameters defining the four boundary lines on the I/V- curves (ideally, the pulsed I/V curves measured from the dc operating point of interest should be used) must also be defined in the Modeling and Modification module. The defined boundary lines are also displayed graphically for verification purposes.
An ADW circuit file can be created for the transistor of interest. If a model was fitted or specified for the transistor, noise parameters can also estimated for the transistor when this is done (Fukui, Pucel or Pospiezalski noise models). The estimated noise parameters are appended to the circuit file created. A nodal description of the model is also written to the file when a model was specified or fitted.
Load-pull data for power transistors can be converted into an equivalent set of unilateral S-parameters in order to allow synthesis of power amplifiers by following the normal ADW synthesis procedures. Feedback should not be used when this is done.
Adding modification networks to a transistor (adding feedback and/or loading sections to a transistor in order to pre-condition it before the matching networks are synthesized) is often the most important step in the design of an amplifier stage. Extensive modification capabilities are provided in the Modeling and Modification Module. Transistors can be stabilized easily, gain slopes can be modified or leveled, and the VSWRs can be improved before (lossless) matching. Transistors can also be modified to reduce the difference between an optimum noise match and an optimum gain match on the input side and/or to reduce the difference between an optimum gain match and an optimum power match on the output side.
Modification can be done with current-series feedback, voltage-shunt feedback and/or shunt or series loading. At least two modification sections are usually required to modify a transistor optimally. The modification technique implemented can automatically combines two modification sections of different types, or two sections of the same type but on different sides of the transistor. When this double-section modification capability is used, a systematic search is done for the components that will level or slope the overall transducer power gain (GT) | the available power gain (Ga ) | the available power gain associated with the optimum noise figure of the modified transistor (Ganopt) | the operating power gain (Gw) | the MAG or the MSG of the amplifier synthesized up to that point (with the gain of the stage designed included). The input or the output VSWRs for the stage designed are controlled directly at the same time.
When modification networks are synthesized, the required gain slope, the range of acceptable gain values, the weight factors, the breakpoints and the zero-error points for the VSWRs, the noise figure and the degree of difficulty of the noise matching problem, the passband over which the gain must be leveled, the VSWR circles of interest, and the angular step to be used on these and the relevant constant gain circles must be specified. The output power, the Rollette stability factor, and the source and load stability factors (SSF, LSF) can also be included in the error function. The stability over the complete range for which parameters were specified or limited to the passband of interest can be considered. With the error function defined, solutions are synthesized to provide the targeted gain and the targeted VSWR at (at least) one of the passband frequencies. These solutions are then screened for suitable performance over the passband of interest by using the error function defined.
The search can be done for a specific double-section modification topology, or a global search can be done. When a global search is done, the option to not use voltage-shunt feedback combinations is also provided. This is often useful when a packaged transistor is used. When the double-section modification section is entered with some modification sections already in place, the list of modification topologies is reduced automatically (Any specific modification section can only be used once).
The gain controlled during device modification is important. If the operating | available power gain of an amplifier stage is controlled, no lossless gain control network will implicitly be used on the output | input of the stage being designed, but a matching network will be required on the input | output side. If the MAG is controlled, matching networks will be required at the input and the output sides of the modified transistor. If the transducer power gain is controlled, no lossless matching networks will be required (It is often possible to eliminate the need for any lossless matching networks in an amplifier totally at the lower frequencies). If the available power gain associated with an optimum noise match is controlled, matching networks will be required on both sides of the transistor. In this case, the input network will be used to minimize the noise figure, while the output network will be used to maximize the gain.
The connecting lines and/or pads required for the transistor and the lumped components can be specified before a modification network is synthesized. When a microstrip substrate is used, a rendering of the connecting line and pad specifications can be displayed graphically for verification purposes. This feature is also useful as an aid to decide whether the lines/pads specified are long enough. In addition to the connecting lines and pads, the following parameters can also be specified:
All of these parasitics are taken into account when double-section modification networks are synthesized.
Thin-film resistors can also be used in the device-modification section. The option to use one or two resistors in any voltage-shunt feedback loop is also provided. If a single resistor is used, it can be positioned at the input or the output side of the feedback loop.
General analysis and optimization capabilities are also provided in the Modeling and Modification Network Module. The potential performance of the (modified) transistor can be evaluated and s11 , s21, s22 , 1/s11* , 1/s22*, the optimum noise impedance, the noise figure and the VSWRs can be displayed graphically.
The maximum linear output power can also be calculated in the Modeling and Modification Network Module. The maximum output power associated with the transducer power gain (modified transistor directly terminated in the stage terminations), the operating power gain (stage load termination used, input conjugately matched), the available power gain (source termination for the stage and a conjugate match at the output), the MAG (conjugate match on both sides), the optimum noise match and a conjugate match at the output, as well as the optimum power match can be calculated for the modified transistor.
The error function used during optimization is the same as that used in the double-section modification section. If required, variables can be fixed or constrained during the optimization.
If the modification problem was set up by using the MOT Wizard in the Analysis Module, the modification network synthesized can also be inserted automatically at the correct position in the circuit file. A separate ADW circuit file can also be created for the modification network. The exported modification network can be imported into the Modification Section again at a later stage, as long as the topology was not changed and the .xsp file created with the circuit file is still present.
The last modification network designed is stored for future use (.cmp file) when the Modeling and Modification Module is closed.
Note that the Modeling and Modification Network Module are integrated in the Amplifier Design Wizard.
The Microstrip Module is used to calculate the characteristic impedance, the effective dielectric constant, the attenuation associated with conductor and dielectric losses, the equivalent line length associated with an open-end and the physical length of a quarter wavelength line. This can be done for different line widths and substrates, at the frequency specified. The relevant parameters can also be calculated for specified values of the characteristic impedances or the line widths. This module can also be used to calculate the parasitics associated with a T-junction when a symmetrical main line is used, as well as the equivalent inductance of a pad with a single via hole in it.
The Microstrip Module was integrated into the different sections of the Amplifier Design Wizard.